The present invention is generally directed to a pulse repetition rate check circuit. It is particularly directed to a pulse repetition rate check circuit which provides an error signal in response to the second of two consecutive pulses provided by a pulse generator being early, late or never occurring with respect to a predetermined repetition time period following the first pulse.
There are many applications where precise timing of digital equipment is absolutely essential. Such equipment is usually operatively timed by a chain of timing pulses which must be properly spaced in time to assure correct operation of the equipment. To assure that such equipment is properly timed, pulse repetition rate circuits have been provided for detecting when the timing pulses are not equally spaced to indicate improper operation of the digital equipment.
Prior art pulse repetition check circuits have included circuits which provide an average repetition rate, that is to say, the timing pulses are counted for a preset time period and an average repetition rate calculated. Obviously, such circuits are inadequate when the repetition rate of the timing pulses must remain constant from one pulse to the next.
Circuits to monitor the repetition rate of a train of timing pulses on a pulse to pulse basis usually include a counter which is responsive to the first of two consecutive pulses for timing the occurrence of the second pulse. Unfortunately, such circuits have experienced difficulty in resetting the counter to accommodate the next pulse in the train where the timing pulses occur at a relatively high repetition rate. It is possible that a pulse may be missed if it occurs within the time required to reset the counter.
Among other functions the counters are generally used for the enabling of an early pulse detector during a predetermined time so that a second pulse occurring within that predetermined time may be detected as an early pulse. Because the counters are generally driven by a free running oscillator and have a finite capacity, there is a possibility that a late pulse may be detected as an early pulse. This could happen, for example, if the second pulse occurs after the counter has counted to capacity and back to zero.
It is therefore a general object of the present invention to provide an improved pulse repetition rate check circuit.
It is a further object of the present invention to provide a pulse repetition rate check circuit which provides an error indication when the second of two consecutive pulses is early, late or never occurs with respect to a predetermined repetition time period which is spaced apart in time by a predetermined time from the first pulse.
It is a still further object of the present invention to provide a pulse repetition rate check circuit which monitors the repetition rate of the pulses generated by a pulse generator on a pulse to pulse basis.
It is a still more particular object of the present invention to provide a pulse repetition rate check circuit which is always ready to accommodate each pulse of a pulse train regardless of the repetition rate of the pulse train.
It is a still further more particular object of the present invention to provide a pulse repetition rate check circuit which includes an early pulse detector which is enabled for a predetermined time so that a second pulse occurring within the predetermined time is detected as an early pulse and wherein the early pulse detector is prevented from being enabled after it has been once enabled to thereby prevent a late pulse from being detected as an early pulse.